Power inverter

ABSTRACT

In a power converting apparatus including a capacitor connected in series which serves to divide a DC voltage, and a PWM inverter bridge for converting the DC voltage into an AC phase voltage having three electric potentials of a positive voltage, a negative voltage and an intermediate voltage in a plurality of phases, a zero voltage period generator ( 11 ) is switched by signal switching devices ( 5  to  10 ) when a load current reaches a first overcurrent level based on the detection of an overcurrent detector ( 12 ), and there is provided a zero voltage period having an intermediate voltage in which output phase voltages having all phases of the power converting apparatus become the intermediate voltages, thereby carrying out a current limitation. With an inexpensive structure, consequently, a rapidly increased current in an inverter can be instantaneously suppressed at time of the detection of an overcurrent.

TECHNICAL FIELD

[0001] The present invention relates to an inverter servo drive forcarrying out a variable speed driving operation for a motor and a powerconverting apparatus for system interconnection.

BACKGROUND ART

[0002] As shown in FIG. 10, an inverter of a three-phase neutral clamptype has such a structure that an inverter bridge having four switchelements and two clamp diodes per phase is used and an intermediatevoltage divided equally by a capacitor having a DC bus voltage connectedin series can be output to a phase output terminal. When S1 and S2 areON and S3 and S4 are OFF in four switch elements connected in series, aphase output terminal voltage is positive. When the S3 and the S4 are ONand the S1 and the S2 are OFF, the phase output terminal voltage isnegative. When the S2 and the S3 are ON and the S1 and the S4 are OFF,the phase output terminal voltage is an intermediate voltage.Accordingly, the S1 and S3 and the S2 and S4 are not turned ON at thesame time. In many cases, therefore, the ON/OFF signal of the S2 isobtained by inverting the signal of the S1 and that of the S4 isobtained by inverting the signal of the S2.

[0003] However, a switching element and a driving circuit have a delay.There is a possibility that respective switches might be simultaneouslyturned ON by the delay and a large short-circuit current might flow tothe switch element to be broken. In consideration of the delay,therefore, a dead time generating circuit shown in FIG. 11 is providedin a controller and the actual ON/OFF signal of the switch element isalways provided with a dead time period to be a simultaneous OFF periodshown in FIG. 12. APWM generator in FIG. 11 generates PWM pulse signalshaving respective phases (U1, U2, V1, V2, W1, W2) based on a command ofan output voltage created in the controller. In the inverter of thethree-phase neutral clamp type, the PWM pulse signal is to be generatedby a set of the S1 and S3 and a set of the S2 and S4. For this reason,each of the PWM pulse signals makes a signal such that the S1 and S3 andthe S2 and S4 are not turned ON at the same time by an invertingcircuit, a delay circuit and an AND gate, and each of the switches isdriven in response to an ON/OFF signal so that the switch element can beprevented from being short-circuited. Also in the case in which a loadcurrent is equal to or larger than a current which can be caused to flowby the switch element, moreover, there is a possibility that the switchelement might be broken. For this reason, it is necessary to provide aprotecting device for detecting a current flowing to a switch elementand turning OFF the switch to carry out a stop.

[0004] Such a protecting method has been proposed in JP-A-10-164854 andJP-A-11-32426.

[0005]FIG. 13 is a diagram showing the structure of a power converterdisclosed in the JP-A-10-164854. Currents flowing to switching elements3A to 3D are monitored by short-circuit detecting and breaking circuits5A and 5B and short-circuit detecting circuits 6A and 6B respectively,thereby detecting a power short-circuit and a load current abnormality.When the abnormality is detected, the switching elements 3A and 3D areturned OFF in a later timing than a normal timing in accordance with thebreaking operations of the short-circuit detecting and breaking circuits5A and 5B and a gate signal sent from a gate control section 16, andthen, one of the switching elements 3B and 3C is turned ON and the otheris turned OFF in a later timing than the normal timing.

[0006] However, a processor is generally used for a controller forcontrolling an inverter to carry out a control by software. Therefore, acontrol for suppressing a load current cannot be carried out by thesoftware of the controller on such a condition that the load currentrapidly becomes an overcurrent in a short time as in a PWM cycle. Forthis reason, as for the rapid increase in the load current, the loadcurrent is to be suppressed at a high speed or the switching of theinverter is to be stopped without using a processor.

[0007] The JP-A-10-164854 and the JP-A-11-32426 have proposed a methodof safely stopping switching without breaking the switch element of theinverter in the overcurrent. However, there have been problems in that arapidly increased load current cannot be controlled and a special delaycircuit and a circuit for carrying out a complicated ON/OFF operationare required for the driving signal system of the switch element.

DISCLOSURE OF THE INVENTION

[0008] Therefore, it is an object of the invention to provide aninexpensive and safe power converting apparatus capable of reliablysuppressing a rapidly increased current instantaneously with such asimple structure as comprising a switching device and a PWM patterngenerator without need of a special delay circuit or a complicatedcircuit.

[0009] In order to attain the object, a first aspect of the invention isdirected to a power converting apparatus comprising a capacitorconnected in series which serves to divide a DC voltage, a positive sidemain switching element and a positive side auxiliary switching elementwhich have three electric potentials for setting the DC voltage to be apositive voltage, a negative voltage and an intermediate voltage byutilizing a node of the capacitor, and are inserted between the positivevoltage side and an output terminal connected to a load and areconnected to each other in series, a negative side main switchingelement and a negative side auxiliary switching element which areinserted between the negative voltage side and the output terminal andare connected to each other in series, a clamp diode connected betweenthe intermediate voltage point and a node of the positive side mainswitching element and the positive side auxiliary switching element andbetween the intermediate voltage point and a node of the negative sidemain switching element and the negative side auxiliary switchingelement, and a free wheel diode which is connected in parallel with eachof the switching elements, and having, in a plurality of phases, a PWMinverter bridge for converting the DC voltage into an AC phase voltagehaving three electric potentials, wherein there is provided a zerovoltage period having an intermediate voltage in which output phasevoltages having all phases of the power converting apparatus become theintermediate voltage when a load current reaches a first overcurrentlevel.

[0010] Moreover, a second aspect of the invention is directed to thepower converting apparatus according to the first aspect of theinvention, wherein three periods having a positive zero voltage periodin which the output phase voltages having all the phases of the powerconverting apparatus become the positive voltage, a negative zerovoltage period in which the output phase voltages having all the phasesof the power converting apparatus become the negative voltage, and azero voltage period having the intermediate voltage are selected andoutput alternately after the zero voltage period 1.

[0011] Furthermore, a third aspect of the invention is directed to thepower converting apparatus according to the second aspect of theinvention, wherein a transition from the positive zero voltage period tothe negative zero voltage period and a transition from the negative zerovoltage period to the positive zero voltage period are prohibited.

[0012] Moreover, a fourth aspect of the invention is directed to thepower converting apparatus according to the first aspect of theinvention, wherein a reset to a normal PWM pulse is carried out when aload current is more than the first overcurrent level and is then lessthan the first overcurrent level.

[0013] Furthermore, a fifth aspect of the invention is directed to thepower converting apparatus according to the fourth aspect of theinvention, wherein a zero voltage period having the intermediate voltageis always output immediately before the normal PWM pulse is output.

[0014] Moreover, a sixth aspect of the invention is directed to thepower converting apparatus according to the fifth aspect of theinvention, wherein a time of the zero voltage period having theintermediate voltage to be output immediately before the output of thenormal pulse is set to be equal to or shorter than a dead time.

[0015] Furthermore, a seventh aspect of the invention is directed to thepower converting apparatus according to any of the fourth to sixthaspects of the invention, wherein a pattern of the normal PWM pulseafter the reset is switched corresponding to a PWM pulse when the loadcurrent reaches the first overcurrent level.

[0016] Referring to such a power converting apparatus, first of all, thePWM pulse will be described by taking a general three-phase two-levelPWM inverter as an example. As shown in FIG. 8 of FIGS. 8 and 9 to beexplanatory diagrams showing a zero voltage vector, the PWM pulseusually compares one triangular-wave carrier with command voltages A, Band C having three phases (U, V, W), thereby creating PWM pulses havingrespective phases. In the drawing, On, Op, a and b represent the namesof output voltage vectors.

[0017] On the other hand, P, N and O indicate a switch state in whicheach vector is converted to ON/OFF of the switch element, P indicates aswitch state in which the phase output terminal of an inverter isconnected to a positive bus, N indicates a switch state in which thesame phase output terminal is connected to a negative bus and Oindicates a switch state in which the same phase output terminal isconnected to a neutral conductor, and PA, PB and PC indicate PWM pulseoutputs having respective phases (U, V, W).

[0018] Moreover, vectors On and Op indicate a state in which a linevoltage short-circuiting the U, V and W phases outputs a zero voltagevector (a zero voltage vector), Op indicates a state in which threeswitches on a positive bus side are ON, and On indicates a state inwhich three switches on a negative bus side are ON.

[0019] When the zero voltage vector is output, a voltage applied to aload is zero so that a load current is decreased. If a potentialdifference between the phases is forcibly set to be zero in anovercurrent, accordingly, a motor current is decreased so that an outputcurrent can be limited.

[0020] While the example of the three-phase and two-level inverter hasbeen described above, a three-phase and three-level inverter may beused. If the zero voltage period generator instantaneously turns OFF theS1 having each phase and turns ON the switch state of the S2 in a fullzero state to set a potential difference between the phases (U, V, W) tobe zero and to set a voltage applied to a load to be zero when theovercurrent of the inverter is detected, a surge voltage applied byswitching is also lessened, a load current is decreased and anovercurrent can be suppressed instantaneously.

BRIEF DESCRIPTION OF THE DRAWINGS

[0021]FIG. 1 is a block diagram showing a power converting apparatusaccording to a first embodiment of the invention,

[0022]FIG. 2 is a diagram showing a PWM pulse illustrated in FIG. 1,

[0023]FIG. 3 is a diagram showing a PWM pulse according to a secondembodiment of the invention,

[0024]FIG. 4 is a diagram showing a PWM pulse according to a thirdembodiment of the invention,

[0025]FIG. 5 is a diagram showing the case in which the currentlimitation operating point of the PWM pulse illustrated in FIG. 4 isdifferent,

[0026]FIG. 6 is a diagram showing a PWM pulse according to a fourthembodiment of the invention,

[0027]FIG. 7 is a diagram showing the case in which the currentlimitation operating point of the PWM pulse illustrated in FIG. 6 isdifferent,

[0028]FIG. 8 is an explanatory diagram showing a PWM pulse according tothe invention,

[0029]FIG. 9 is a diagram showing the case in which the voltage commandof the PWM pulse illustrated in FIG. 8 is shifted,

[0030]FIG. 10 is a circuit diagram showing a conventional inverter of athree-phase neutral clamp type,

[0031]FIG. 11 is a block diagram showing a dead time generating circuitof the inverter illustrated in FIG. 10,

[0032]FIG. 12 is a diagram for explaining the concept of a dead timeillustrated in FIG. 11, and

[0033]FIG. 13 is a diagram showing the structure of a well-known powerconverter.

[0034] In the drawings, 1 denotes a PWM pulse generator, 2 to 4 denote adead time generating circuit block, 5 to 10 denote a switching device,11 denotes a zero voltage period generator, and 12 denotes anovercurrent detector.

BEST MODE OF CARRYING OUT THE INVENTION

[0035] Next, a first embodiment of the invention will be described withreference to the drawings.

[0036]FIG. 1 is a block diagram showing a power converting apparatusaccording to the first embodiment of the invention.

[0037]FIG. 2 is a diagram showing a PWM pulse illustrated in FIG. 1.

[0038] In FIG. 1, 1 denotes a PWM signal generator which generates a PWMpulse by a comparison of a triangular wave carrier with a voltagecommand or a calculation.

[0039] Numerical references 2 to 4 denote the same dead time generatoras that in the conventional art, which inverts PWM pulses (U1, U2, V1,V2, W1, W2) and outputs ON/OFF signals S1 u to S4 w of a switch elementthrough a delay circuit and an AND gate to each switch element,respectively. Numerical references 5 to 10 denote a signal switchingdevice of the PWM signal generator 1 and a zero voltage period generatorwhich switches the PWM pulse signal by a PWM pattern switching signal.Numerical reference 11 denotes the zero voltage period generator whichoutputs a zero voltage to be an intermediate voltage in place of the PWMpulse. 12 denotes an overcurrent detector such as a current detector.

[0040] The overcurrent detector 12 fetches currents having U, V and Wphases of an inverter output and the current of the inverter monitors anovercurrent level 1 (which is preset), and a signal sent from acomparator (not shown), indicating whether or not the overcurrent level1 is exceeded, is transmitted to the zero voltage period generator 11.The zero voltage period generator 11 turns OFF the signals U1, V1 and W1and turns ON the signals U2, V2 and W2, and generates a zero voltagesignal setting each phase voltage to be an intermediate voltage.

[0041] Next, an operation will be described.

[0042] In the first embodiment, the zero voltage period generator 11previously outputs a zero voltage signal having an intermediate voltageand instantaneously switches the signal switching devices 5 to 10 fromthe signal of the PWM signal generator 1 to that of the zero voltageperiod generator 11 upon receipt of a signal sent from the overcurrentdetector 12. In order to cause the voltage having each phase to be equalfor a zero voltage period, it is preferable that the zero voltage periodgenerator 11 should output only S1 and S2 signals having the respectivephases. In the case in which the current of the inverter flows in alarge amount, thus, a voltage applied to the inverter becomes zero whenan output line voltage is instantaneously set to be a zero voltage byhardware. Consequently, a load current is decreased so that anovercurrent can be suppressed.

[0043] Moreover, a zero potential to be output is set to be anintermediate voltage for each phase. Therefore, there is neither asituation switching from a state in which the switch elements S1 and S2are simultaneously turned ON to a state in which they are simultaneouslyturned OFF nor a situation switching from a state in which S3 and S4 aresimultaneously turned ON to a state in which they are simultaneouslyturned OFF. Consequently, it is possible to obtain an advantage that asurge voltage applied to the switch element and the load is reduced.

[0044] In the case where an overcurrent suppressing operation is carriedout and a current is thereafter decreased to be less than theovercurrent level 1, the zero voltage period generator 11 monitors thesignal of the carrier signal generator of the PWM generating section 1and the signal of the overcurrent detector 12, and, at time of the nextPWM pattern being updated, it cancels the overcurrent suppressingoperation so as to output a normal PWM pattern and to continuously carryout an operation. Consequently, it is possible to alleviate a shock anda surge voltage which are caused by switching the PWM pattern, therebyperforming a safe load driving operation.

[0045] The operation will be specifically described with reference toFIG. 2. Referring to a PWM pattern in FIG. 2, FIG. 2(a) showing a PWMpattern in a normal state is compared with FIG. 2(b) showing an exampleof a PWM pattern in the overcurrent suppressing operation according tothe first embodiment. FIG. 2 illustrates only a PWM patterncorresponding to one phase. During a current limitation, all phasesoutput the same voltage. A triangular wave to be generally used as a PWMcarrier of the carrier signal generator provided in the PWM generator 1will be taken as an example. Moreover, there is conceptually shown thata cycle of the vertex and the lowest point of the PWM carrier is a halfof the PWM cycle and an update point of the PWM pattern.

[0046] The PWM pulse is represented as N, O and P of a vector mode. Pindicates a state in which the S1 and the S2 are ON and the S3 and theS4 are OFF, N indicates a state in which the S3 and the S4 are ON andthe S1 and the S2 are OFF, and O indicates a state in which the S2 andthe S3 are ON and the S1 and the S4 are OFF. During a currentlimitation, the S1 is OFF for all phases and the S2 is ON for all thephases. A zero voltage output for setting a switch state to be afull-phase O state is obtained. When the current limitation iscancelled, moreover, a reset to the same (NOPPON) normal PWM patternoutput as that in FIG. 2(a) is carried out.

[0047] Next, a second embodiment of the invention will be described withreference to the drawings.

[0048]FIG. 3 is a diagram showing a PWM pulse according to the secondembodiment of the invention.

[0049] In the second embodiment, the block diagram of FIG. 1 is commonlyapplied to the embodiment described above. A zero voltage periodgenerator 11 once sets a voltage having each phase to be an intermediatevoltage, and sequentially switches all phases in order of anintermediate voltage—a positive voltage—the intermediate voltage, andthe intermediate voltage—a negative voltage—the intermediate voltage(OPO, ONO) during a current limitation after a next PWM pattern update,and outputs them. Consequently, there is no switching into the positivevoltage—the negative voltage (PN) and the negative voltage—the positivevoltage (NP). Therefore, there is neither switching from a state inwhich switch elements S1 and S2 are simultaneously turned ON to a statein which they are simultaneously turned OFF nor switching from a statein which S3 and S4 are simultaneously turned ON to a state in which theyare simultaneously turned OFF. Thus, it is possible to obtain anadvantage that a surge voltage applied to the switch element and a loadcan be reduced.

[0050]FIG. 3 shows an example of the PWM pattern (corresponding to onephase). Although FIG. 3 illustrates only the PWM pattern for one phase,all phases output the same voltage during a current limitation. In theembodiment described above, all the phases are set to be theintermediate voltage (the S1 and the S4 are turned OFF, and the S2 andthe S3 are turned ON) during the current limitation. Therefore, there isa possibility that a load current exceeding an overcurrent level 1 mightcontinuously flow in the switch element S2 or S3 and the switch elementS2 or S3 might be broken due to heat generated by a conduction loss. Inthe second embodiment, however, the load current flows in the S2 or S3with switching. Consequently, the conduction loss is decreased so thatthe switch element can be prevented from being broken.

[0051] Moreover, it is also possible to carry out an operation forcarrying out switching in order of the intermediate voltage—the positivevoltage—the intermediate voltage or the intermediate voltage—thenegative voltage—the intermediate voltage from the time immediatelyafter the start of the current limitation to the next PWM pattern beingupdated, in the case where a zero voltage period for the intermediatevoltage is output from a time immediately after the start of the currentlimitation to the next PWM pattern update.

[0052] Next, a third embodiment of the invention will be described withreference to the drawings.

[0053]FIG. 4 is a diagram showing a PWM pulse according to the thirdembodiment of the invention.

[0054]FIG. 5 is a diagram showing the case in which the currentlimitation operating point of the PWM pulse illustrated in FIG. 4 isdifferent.

[0055]FIGS. 4 and 5 show a PWM pattern (corresponding to one phase)according to the third embodiment. Although FIGS. 4 and 5 illustrateonly the PWM pattern for one phase, all phases output the same voltageduring a current limitation. FIG. 1 is a common diagram.

[0056] In an example according to the third embodiment shown in FIG. 4,a current limiting operation is always cancelled on the vertex of a PWMcarrier when a load current enters the current limiting operation in thecase where the triangular wave of the PWM carrier is moved from thelowest point toward the vertex (FIG. 4a is the same as FIG. 3).

[0057] In FIGS. 4(b) and 4(a), time periods required from a time that anovercurrent detector 12 has a normal value again to a current limitingcancellation are different from each other.

[0058] In the example shown in FIG. 5, the current limiting operation isalways cancelled on the lowest point of a PWM carrier when a loadcurrent enters the current limiting operation in the case in which thetriangular wave of the PWM carrier is moved downward from a vertex.

[0059] For example, when the current limiting operation is cancelled ononly the lowest point of the PWM carrier, the PWM pulse isstochastically output most greatly in a PWM pattern in the middle of arise from the lowest point of the PWM carrier to the vertex on such acondition that the current limiting operation and the cancellationthereof are repeated. Consequently, the PWM pulse becomes nonuniform. Incase of an inverter of a three-phase neutral clamp type, there is aproblem in that a current (in of FIG. 10) flowing to the voltagedividing point of a capacitor is imbalanced and the intermediatepotential of the capacitor is increased and greatly gets out of ½ of aDC bus voltage. However, having a configuration as described in thisinvention, the PWM carrier at time of a cancellation starts from anascending pattern if the PWM pulse to be output enters the currentlimiting operation during the descending period of the PWM carrier,while the PWM carrier at time of the cancellation starts from adescending pattern, which is the reversed PWM carrier pattern of theprevious one, if the PWM pulse enters the current limiting operationduring the ascending period of the PWM carrier. Consequently, the PWMpulse to be output is always made uniform on such a condition that thecurrent limiting operation and the cancellation are repeated, and avoltage on the voltage dividing point of the capacitor can be preventedfrom considerably fluctuating.

[0060] In FIGS. 5(a) and 5(b), time periods from a time that theovercurrent detector 12 has a normal value again to the cancellation ofthe current limitation are different from each other.

[0061] Next, a fourth embodiment of the invention will be described withreference to the drawings.

[0062]FIG. 6 is a diagram showing a PWM pulse according to the fourthembodiment of the invention.

[0063]FIG. 7 is a diagram showing an example in which the currentlimitation operating point of the PWM pulse illustrated in FIG. 6 isdifferent.

[0064] FIGS. 6(a) and 7(a) show a PWM pattern (corresponding to onephase) according to the fourth embodiment, and FIGS. 6(b) and 7(b) showthe actual switch driving signal waveforms of S1 to S4.

[0065] Although FIGS. 6 and 7 illustrate only the PWM pattern for onephase, all phases output the same voltage during a current limitation.In FIG. 6, a current limiting operation starts and outputs anintermediate voltage of a zero voltage period. Thereafter, if a PWMcarrier is descending pattern in a next PWM update timing, then “a zerovoltage period having an intermediate voltage which is equal to orshorter than a dead time”—“a positive zero voltage period”—“the zerovoltage period having the intermediate voltage which is equal to orshorter than the dead time” is output. On the contrary, if the PWMcarrier is ascending pattern as shown in FIG. 7, then “the zero voltageperiod having the intermediate voltage which is equal to or shorter thanthe dead time”—“a negative zero voltage period”—“the zero voltage periodhaving the intermediate voltage which is equal to or shorter than thedead time” is output. During a current limiting period, thus, the ON/OFFtimes of S1 and S2, and S3 and S4 have a difference which is an almostdouble of the dead time, and they are almost equal to each other.Consequently, the conduction losses of the switch elements S1 to S4 arealmost equal to each other so that the S2 and S3 can be prevented frombeing broken by heat.

[0066] Moreover, the zero voltage period having the intermediate voltageis equal to or slightly shorter than the dead time. Therefore, a shortpulse in an equal time to the dead time which is generated in thecancellation of the current limiting operation is suppressed by theaction of a dead time generating circuit. When a pulse which is equal toor slightly shorter than the dead time is suppressed, thus, it ispossible to prevent some of the switching elements from being extremelyincreased the number of switching operations with repeating theoperation of the current limiting operation and the cancellation.Consequently, it is possible to prevent the switch element from beingbroken due to the over heat caused by the switching loss.

[0067] Contrary to this example, after outputting an intermediatevoltage of a zero voltage period, and if a PWM carrier is ascendingpattern in a next PWM update timing, then “a zero voltage period havingan intermediate voltage which is equal to or shorter than a deadtime”—“a positive zero voltage period”—“the zero voltage period havingthe intermediate voltage which is equal to or shorter than the deadtime” is output. On the contrary, if the PWM carrier is descendingpattern as shown in FIG. 7, then “the zero voltage period having theintermediate voltage which is equal to or shorter than the dead time”—“anegative zero voltage period”—“the zero voltage period having theintermediate voltage which is equal to or shorter than the dead time” isoutput. Also in this case, the same advantages can be obtained.

[0068] The zero voltage period generator 11 for carrying out theoperation according to the invention is equivalent to the PWM generator1 for outputting the same PWM pulses for three phases. Therefore, thePWM generator 1 can be also caused to have the function comparativelyeasily. In this case, the zero voltage period generator can be omittedand the invention can be implemented by a simpler circuit.

[0069] While the invention has been described in detail by referring tothe specific embodiments, it is apparent to the skilled in the art thatvarious changes and modifications can be made without departing from thespirit and scope of the invention.

[0070] The application is based on Japanese Patent Application (No.2001-200843) filed on Jul. 2, 2001, and the contents thereof areincorporated by reference.

[0071] Industrial Applicability

[0072] As described above, according to the invention, it is possible toobtain an advantage that a rapidly increased current can be suppressedinstantaneously by only a simple switching device and a PWM patterngenerator using a power converting apparatus having a PWM pulsegenerating method of an inverter provided with a zero voltage period inan overcurrent, and the control circuit of the inverter is inexpensiveand a safety can be enhanced.

[0073] Furthermore, the current limiting operation is always cancelledon the lowest point of the PWM carrier when the current limitingoperation starts in the case in which the triangular wave of a PWMcarrier is brought down from a vertex, and is always cancelled on thevertex of the PWM carrier when the current limiting operation starts inthe case in which the triangular wave is raised from the lowest point.Thus, the PWM pattern is switched in the cancellation of the currentlimiting operation according to the PWM pattern in which the currentlimiting operation starts. Consequently, it is possible to obtain anadvantage that a neutral potential can be prevented from fluctuating dueto the nonuniformity of the PWM pulse.

[0074] In addition, the zero voltage period to have the intermediatevoltage to be applied immediately before the output of a normal PWMpulse is equal to or shorter than the dead time. Therefore, theconduction losses of the switch elements are equal to each other and theswitch element can be prevented from being broken due to heat.

1. A power converting apparatus comprising a capacitor connected in series which serves to divide a DC voltage, a positive side main switching element and a positive side auxiliary switching element which have three electric potentials for setting the DC voltage to be a positive voltage, a negative voltage and an intermediate voltage by utilizing a node of the capacitor, and are inserted between the positive voltage side and an output terminal connected to a load and are connected to each other in series, a negative side main switching element and a negative side auxiliary switching element which are inserted between the negative voltage side and theoutput terminal and are connected to each other in series, a clamp diode connected between the intermediate voltage point and a node of the positive side main switching element and the positive side auxiliary switching element and between the intermediate voltage point and a node of the negative side main switching element and the negative side auxiliary switching element, and a plurality of free wheel diodes which is connected in parallel with each of the switching elements, and having, in a plurality of phases, a PWM inverter bridge for converting the DC voltage into an AC phase voltage having three electric potentials, wherein there is provided a zero voltage period having an intermediate voltage in which output phase voltages having all phases of the power converting apparatus become the intermediate voltage when a load current reaches a first overcurrent level.
 2. The power converting apparatus according to claim 1, wherein three periods having a positive zero voltage period in which the output phase voltages having all the phases of the power converting apparatus become the positive voltage, a negative zero voltage period in which the output phase voltages having all the phases of the power converting apparatus become the negative voltage, and a zero voltage period having the intermediate voltage are selected and output alternately after the zero voltage period.
 3. The power converting apparatus according to claim 2, wherein a transition from the positive zero voltage period to the negative zero voltage period and a transition from the negative zero voltage period to the positive zero voltage period are prohibited.
 4. The power converting apparatus according to claim 1, wherein a reset to a normal PWM pulse is carried out when a load current is more than the first overcurrent level and is then less than the first overcurrent level.
 5. The power converting apparatus according to claim 4, wherein a zero voltage period having the intermediate voltage is always output immediately before the normal PWM pulse is output.
 6. The power converting apparatus according to claim 5, wherein a time of the zero voltage period having the intermediate voltage to be output immediately before the output of the normal pulse is set to be equal to or shorter than a dead time.
 7. The power converting apparatus according to any of claims 4 to 6, wherein a pattern of the normal PWM pulse after the reset is switched corresponding to a PWM pulse when the load current reaches the first overcurrent level. 